1. Field of the Invention
The present invention relates to a fundamental cell that constitutes a basic unit in the layout of a semiconductor integrated circuit device, a semiconductor integrated circuit device which uses such fundamental cells, a wiring method as well as a wiring apparatus thereof, and more particularly to a fundamental cell that may be used in a semiconductor integrated circuit device of the gate array type and standard array type, a semiconductor integrated circuit device that uses such fundamental cells, and a wiring method as well as wiring apparatus thereof.
2. Description of the Related Art
A semiconductor integrated circuit device of the gate array type and standard cell type is used so far, in which functional circuit blocks constituted of fundamental cells in a matrix structure are arranged. FIG. 12 shows a typical example of a fundamental cell 100. The fundamental cell 100 has therein a power supply voltage wiring VOD and ground potential wiring VSS, or so-called the power rails VOD and VSS in order to supply the power supply voltage VDD and ground potential VSS respectively to the fundamental cell 100. Connection terminals 2 and 3 are used for biasing N-type well region of a PMOS (P-channel metal oxide semiconductor) transistor and a P-type well region of an NMOS (N-channel metal oxide semiconductor) transistor to the power supply voltage VDD and the ground potential VSS, respectively.
When the power rails VDD and VSS or the connection terminals 2 and 3 are placed fixedly in the fundamental cell 100, if the fundamental cells 100 are arranged in a matrix (see also FIG. 13 and FIG. 14), the power rails VDD and VSS or the connection terminals 2 and 3 will be placed in a predetermined wiring track. Thus the power rails VDD and VSS have been designed to include the connection terminals 2 and 3 between fundamental cells 100 so as to coincide with the wiring track specification of the fundamental cell 100 in the row direction of the fundamental cells 100 (direction lateral to the fundamental cells 100) in each fundamental cell 100. The power rails VDD and VSS will be made at the same time as the fundamental cells 100 are arranged in a matrix so as to constitute a functional circuit block 200. As shown in FIG. 14, the power rails VDD and VSS will be wired in parallel to the wiring track along with the row direction of the fundamental cells 100 (lateral to the fundamental cells 100) when the fundamental cells 100 are placed. The power rails VDD and VSS are, in general, so important wirings for operating the circuit that the wirings are Performed with metal wiring layer M1, the lowest layer.
However, in the fundamental cell 100 in accordance with the Related Art as have been described above, the wirings of the power rails VDD and VSS will be completed at the same time as the fundamental cells 100 are arranged in a matrix so as to form a functional circuit block, however, there will be problems that the wiring direction, width of wirings, the wiring layer of the power rails VDD and VSS cannot be moved or changed from the lowest metal wiring layer M1.
Now referring to FIG. 13, there is shown a layout example of four fundamental cells 100A, 100B, 100C, and 100D in a matrix of 2 by 2 grid to form a functional circuit block 200 as shown by the operating circuit in FIG. 3. As can be appreciated clearly from the figure, the power rails VDD and VSS are formed in the lowest metal wiring layer M1, in a predetermined width of wirings along with the wiring track extending in the row direction from the fundamental cell 100A to the fundamental cell 100D (lateral direction extending from the fundamental cell 100A to the fundamental cell 100D). In other words, the power rails VDD and VSS are wired and formed in the lowest metal wiring layer M1 between the outputs of the fundamental cell 100C forming a NOR1 and the fundamental cell 100D forming a NOR2, and the given gates of the fundamental cells 100A and 100B forming NAND1 having these outputs as input. In the semiconductor integrated circuit devices of the gate array type and standard cell type, in general, upper metal wiring layers are used for wiring between functional circuit blocks, and the signal wirings within a functional block are made by using the lowest metal wiring layer M1 together with the power rails VDD and VSS. The connection between NOR1 and NAND1 and the connection between NOR2 and NAND1 need to bridge over the power rails VDD and VSS formed in the lowest metal wiring layer M1, by routing through the metal wiring layer M2 through VIA 101A and 101C, and through VIA 101B and 101D, respectively. When the functional circuit block is much larger, the wirings need to bridge over the power rails VDD and VSS more often to spoil the degree of freedom of metal wirings and to complicate the structure of metal wirings. In addition, the number of wirings in the upper metal wiring layer M2 will become numerous to narrow the wiring space in the upper metal wiring layer M2. When wiring other signal lines using the same wiring layer, while having the power rails VDD and VSS fixed to fundamental cells 100, the number of wiring tracks is required to increase as much as needed to finally increase the cell height of fundamental cell 100. This may cause another problem of disturbance in the integration of semiconductor integrated circuit device.
Furthermore, as shown in FIG. 14, since the wiring direction, wiring width, and wiring layer of power rails VDD and VSS are fixed, the wiring scheme of power rails VDD and VSS may not be allowed to change so as to conform to the circuit specification of a functional circuit block 300 having fundamental cells 100 (M, N) arranged in a matrix grid (where M and N are integer equal to or more than 1). In other words, there may be cases in which a capability of delivering sufficient power supply for performing desired operation in the functional circuit blocks that operates at a very increased speed or that drives a large load cannot be ensured. In addition, there may be cases in which the wiring pitch is narrower than required to have the potential of delivering power to the loaded functional circuit blocks that consume small current, so that it may interfere higher integration.
In FIG. 14, since the wiring direction, wiring width, and wiring layer of power rails VDD and VSS for fundamental cells 100 (M, N) are fixed, the wiring will be also fixed in the functional circuit block 300 of fundamental cells 100 (M, N) arranged accordingly. When forming a semiconductor integrated circuit device of the gate array type or standard cell type by combining such functional circuit blocks 300, the wiring direction, wiring width, and wiring layer of power rails VDD and VSS in the functional circuit blocks 300 will be inherently fixed. Thus, there may be cases in which functional circuit blocks 300 cannot be arranged so as to conform to the wiring of power rails VDD and VSS around the functional circuit blocks 300, resulting in a problem that a further integration in a semiconductor integrated circuit device of the gate array type and standard cell type will be interfered.
The present invention has been made in view of the above circumstances and has an object to overcome the above problems and to provide a fundamental cell, a semiconductor integrated circuit device, a wiring method thereof and wiring apparatus, allowing a degree of freedom in wirings when designing a layout of functional circuit blocks or a semiconductor integrated circuit device by making use of the fundamental cells.
To achieve the objects and in accordance with the purpose of the invention, as embodied and broadly described herein, one aspect of a fundamental cell, in accordance with the present invention, for forming a basic unit in the layout of a semiconductor integrated circuit device, comprises:
no fixed wiring for commonly wiring between fundamental cells, and
connection terminals to be connected to an upper wiring layers.
In the fundamental cell in accordance with the present invention, no fixed wiring to commonly wire between fundamental cells is incorporated in the fundamental cell, and connecting terminals to connect to other fundamental cells are formed for wiring in an upper wiring layer instead.
In this manner, wiring scheme will not be restricted by the fixed wiring to be wired between fundamental cells, to freely design the wirings. In addition, since no fixed wiring exists the wirings within a functional circuit block may be freely configured or changed in order to avoid the interference between the fixed wiring and other signal wirings on a layout when forming a functional circuit block by arranging fundamental cells. More specifically, in accordance with the present invention, the wiring pattern using the upper layer wirings to bridge over the lower layer wiring may be decreased to the required minimum to ensure the degree of freedom of wiring as much as possible. Therefore, the wiring pattern in accordance with the present invention may achieve a simplest wiring pattern possible, which may not interfere the wiring region in the upper wiring layers.
The wiring to be placed between fundamental cells may be freely configured in the upper wiring layers independent of the wiring within a fundamental cell, so that the requirement of wiring tracks as needed may be ensured while keeping the cell height of the fundamental cell as low as possible when compared with the configuration of both wirings in the same wiring layer. Thus, the present invention may achieve a lower cell height of the fundamental cell together with an efficient wiring scheme to greatly contribute to the higher integration of semiconductor integrated circuit devices. The wiring direction, wiring width and wiring layer of wiring to be placed between fundamental cells may be configured as required by the circuit operation specification of the functional circuit blocks used so that the optimum circuit operation can be attained by the wiring most suitable to the requirement of operation specification of respective circuits. In addition, in the semiconductor integrated circuit device of the gate array type and standard cell type, which need to arrange functional circuit blocks with fundamental cells combined in a matrix structure, the wiring direction, wiring width, and wiring layers of wiring to be placed between fundamental cells may be designed freely in correspondence with the wiring layout made in a functional circuit block, resulting in a wiring layout of functional circuit blocks as effective as possible to realize higher integration of semiconductor integrated circuit devices.
The semiconductor integrated circuit device in one aspect in accordance with the present invention may comprise a fundamental cell, which constitutes a basic unit in the layout design, having no fixed wiring to be placed in common between the basic units, and having connecting terminals to be connected to upper wiring layers, and upper layer wirings of a predetermined wiring direction and a predetermined wiring width appropriately selected for connecting within the upper wiring layer between the connecting terminals of corresponding fundamental cells.
The semiconductor integrated circuit device in accordance with the present invention may be formed by arranging more than two fundamental cells and by connecting the corresponding connecting terminals between the fundamental cells in a predetermined wiring direction and predetermined wiring width preferably selected.
The wiring method in accordance with one aspect of the present invention for wiring a semiconductor integrated circuit device including more than two fundamental cells, which constitutes basic units in the layout design, having no fixed wiring to be placed in common between the basic units, and having connecting terminals to be connected to an upper wiring layers, may comprise the step of wiring upper wirings at first by appropriately selecting the wiring direction and wiring width of upper wiring to be connected within an upper wiring layers between the corresponding connecting terminals of fundamental cells.
The wiring method will wire the upper wiring prior to other wirings by appropriately selecting the wiring direction and wiring width of the upper wirings when connecting the corresponding connecting terminals between fundamental cells in an upper wiring layers.
The wiring method in accordance with another aspect of the present invention for wiring a semiconductor integrated circuit device including more than two fundamental cells, which constitutes basic units in the layout design, having no fixed wiring to be placed in common between the basic units, and having connecting terminals to be connected to upper wiring layers, may comprise the step of wiring the upper wirings in an automatic wiring process together with other wirings.
The wiring method will wire the upper wirings in an automatic wiring process together with other wirings.
In this manner, a semiconductor integrated circuit device will be formed from functional circuit blocks, which allow the internal wiring to be configured and changed as desired by combining the fundamental cells that will not be restricted by the upper wirings to freely draw the wiring pattern and that have upper wirings unfixed, so that the mutual interference between the upper wirings and other signal wirings may be avoided. Then the wiring patterns using the upper layers wiring to bridge over the lower layer wiring may be decreased to the required minimum to ensure the degree of freedom of wiring as much as possible. Therefore, the wiring patterns in accordance with the present invention may achieve a simplest wiring pattern possible, which may not interfere the wiring region in the upper wiring layer. Since the upper wirings may be freely configured as desired in the upper wiring layers independent of the wiring within the fundamental cells, the present invention may provide a semiconductor integrated circuit device, in which the requirement of wiring tracks as needed may be ensured while keeping the cell height of the fundamental cells as low as possible when compared with the configuration of both wirings in the same wiring layer. The wiring direction and wiring width of the upper layer wiring may be configured as required by the circuit operation specification of the functional circuit blocks to be used so that a semiconductor integrated circuit device may be provided to attain the optimum circuit operation by the wiring most suitable to the requirement of operation specification of respective circuits. In addition, the wiring direction, wiring width, and wiring layers of wiring to be placed between fundamental cells may be designed freely as desired in correspondence with the wiring layout made in a functional circuit block, resulting in a wiring layout of functional circuit blocks as effective as possible to realize higher integration of semiconductor integrated circuit devices.
By forming the wiring width of upper layer wirings in a plane beyond the cell height of the fundamental cells, the wiring plane of the power supply voltage or the ground potential may be formed to cover the functional circuit blocks in the semiconductor integrated circuit device for a preferable measure of noise relaxation. In such a case, if more than two upper wiring layers are used then the wiring planes having a multiple plane structure will be formed by designing wiring layers for each different upper layer wiring.
The wiring apparatus in accordance with one aspect of the present invention for achieving the wiring method as have been described above, may comprise:
a cell information storage unit for storing fundamental cell information including the position of connecting terminals;
a wiring information configuration unit for configuring as needed the wiring information with respect to the wiring direction, wiring width, wiring priority, wiring layer of upper layer wirings to connect to corresponding connector terminals of fundamental cells, and a wiring prohibited area in the wiring path;
a wiring information storage unit for storing wiring information configured by the wiring information configuration unit;
a controller unit for performing the wiring process in accordance with the information on the wiring direction, wiring width, wiring priority, and wiring layer stored in the wiring information storage unit and based on the position information of the connector terminals stored in the cell information storage unit for bypassing the wiring prohibited area in the wiring path;
a wiring monitoring unit for monitoring the progress of wiring process performed by the controller unit; and
a wiring data storage unit for storing the resulting wiring process performed by the controller unit.
The wiring apparatus as have been described above will store in the wiring information storage unit the wiring information on the wiring direction, wiring width, wiring priority, and wiring layer of the upper layer wirings for connecting appropriately corresponding connector terminals between fundamental cells and information including the wiring prohibited region in the wiring path, determined by the wiring information configuration unit to use together with the fundamental cell information including the position of connector terminals stored in the cell information storage unit to perform the wiring process by the controller unit. The progress of wiring process will be monitored by the wiring monitoring unit and the resulting wiring process will be stored in the wiring data storage unit.
By the wiring apparatus of the present invention, for performing the wiring on a functional circuit block or on a semiconductor integrated circuit device having more than two fundamental cells arranged, the wiring information of the upper layer wirings may be configured and stored to use the fundamental cell information including the position of connector terminals to monitor the wiring process to be performed, thereby allowing performing an optimum wiring process.
The above and further objects and novel features of the invention will more fully appear from following detailed description when the same is read in connection with the accompanying drawings. It is to be expressly understood, however, that the drawings are for the purpose of illustration only and not intended as a definition of the limits of the invention.